Technical Field
The present invention relates generally to semiconductor devices, and more specifically, to forming semiconductor devices having equal thickness gate spacers.
Description of the Related Art
In CMOS (complementary metal oxide semiconductor) technologies, NFET (n-type field effect transistor) and PFET (p-type field effect transistor) devices are optimized to achieve required design performance. This optimization can include doping concentrations, material selections and dimensions. For example, in conventional CMOS technologies, and particularly in dual epi process schemes for source and drain formation, both the NFET and PEET devices share many of the same processes and topology to reduce manufacturing costs. However, in current process schemes, and in particular dual epi process schemes, the spacer thickness of the NFET and PFET devices are different, with the NFET device having a thicker spacer than the PFET devices. This thicker spacer leads to degraded device performance due to longer proximity to the channel. In addition, as gate pitch scales below 50 nm, there's no room to optimize the device performance with unequal spacer thickness. To provide maximum space for gate and source/drain, spacer thickness is almost close to minimum insulator thickness required for reliability requirement (such as contact to gate breakdown) for both NFET and PFET, and they have to be equal or significantly close in thickness.